Identification of High-Risk Hardware Path-Delay Fault Locations and Evaluation of Their Impact

Ayele, Tadele Basazenew (2014) Identification of High-Risk Hardware Path-Delay Fault Locations and Evaluation of Their Impact. Masters thesis, Addis Ababa University.

[img] PDF (Identification of High-Risk Hardware Path-Delay Fault Locations and Evaluation of Their Impact)
Tadele Basazenew .pdf - Accepted Version
Restricted to Repository staff only

Download (2MB) | Request a copy


Ascertaining correct operation of digital logic circuits requires verification of functional behavior as well as correct operation at desired clock speed. The maximum allowable clock rate in a digital circuit is determined by the propagation delays of the combinational logic network between latches. If the delay of the manufactured network exceeds specifications due to some physical defects or process variations, non-confidential and possibly incorrect logic values may be latched in memory elements. In this thesis, we present novel and efficient model for path delay faults specifically for stack at fault in combinational logic circuits. We propose new and efficient Model for delay fault analysis, test generation and fault simulation of path delay faults in combinational logic circuits. Then the new model was analyzed using reduced order binary decision diagram of the Colorado University Decision Diagram package. An approach for selecting critical paths along which testable path delay faults can exist is presented. The proposed method is particularly helpful on path intensive circuits (large number of paths). Critical paths are selected implicitly with the aid of a combination of decision diagrams. Ideally, all the path delay faults of a circuit should be tested. However, a circuit may have a very large number of paths, making it impossible to target all the path delay faults explicitly during test generation or fault simulation. The large numbers of paths in practical circuits lead to the use of path selection, where only subsets of the path delay faults in circuits are targeted for test generation, in this case only high-risk paths. To reduce our efforts for finding test vectors, which in turn reduce testing memory and processor power and analyzing a circuit for its faults, we try to use reduced faults. Reduced faults can be obtained by eliminating redundant ones and ignoring some that do not occur often or by eliminating faults that have the same output effect by fault collapsing rules.The effectiveness of the approach is demonstrated on path intensive international symposium on circuits and systems (ISCAS'85) and International Transmission Company (ITC'99) benchmarks.

Item Type: Thesis (Masters)
Uncontrolled Keywords: High-risk Paths, Delay Fault Model, ROBDD, Fault reduction
Subjects: H Social Sciences > HE Transportation and Communications
Q Science > Q Science (General)
Q Science > QA Mathematics > QA75 Electronic computers. Computer science
T Technology > T Technology (General)
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Africana
Depositing User: Andriamparany Edilbert RANOARIVONY
Date Deposited: 29 Nov 2018 10:50
Last Modified: 29 Nov 2018 10:50

Actions (login required)

View Item View Item