Ababu, Teshome (2007) Design of Pulse Width Modulation (PWM) and It’s Implementation in Xilinx Field Programmable Gate Array (FPGA). Masters thesis, Addis Ababa University.
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PDF (Design of Pulse Width Modulation (PWM) and It’s Implementation in Xilinx Field Programmable Gate Array (FPGA))
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Abstract
The following thesis describes the design, the synthesis, and the implementation of pulse width modulation (PWM) in Xilinx Field Programmable Gate Array (FPGA). The contribution of this thesis is the development of PWM in Xilinx Integrated System Environment (ISE) CAD tools and The VHDL modeling is used in the design process of PWM. Pulse width modulation has been widely used in many applications especially in communication and control systems. The paper develops high frequency PWM generator architecture for using FPGA. The resulting FPGA frequency depends on the target FPGA speed grade and the duty cycle resolution requirements. In most industrial application due to the need of design integration in control systems FPGA based PWM controller is advantageous over the other controller systems like microprocessor, microcontroller and so on. As geometries shrink and device counts multiply, opportunities abound to do incredible things with in the confines of a single chip (FPGA). Greater focus on design reuse, where earlier design is utilized and reused in later design. The power, compactness and flexibility of the FPGA based controller could be useful in motor control, particularly in robotics where those qualities are important. The FPGA provides advantages over traditional methods such as microcontroller based designs and PLD/ASIC designs by combining the strengths of both. The FPGA allows for implementation of parallel processing for generating the required waveforms. In addition to this the paper describes the architectural features of Xilinx FPGA to the other programmable logic device and explores the design using Very high speed integrated circuit hardware description language (VHDL). The VHDL model was implemented on the Spartan 3e FPGA and optimized for space. The optimized implementation was found to consume 34 numbers of slices, 18 numbers of slice flip flops, 65 numbers of 4 input LUTs and 11 numbers of bonded IOBs.
| Item Type: | Thesis (Masters) |
|---|---|
| Uncontrolled Keywords: | Electrical Engineering |
| Subjects: | Q Science > Q Science (General) Q Science > QA Mathematics > QA75 Electronic computers. Computer science Q Science > QC Physics T Technology > T Technology (General) T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Africana |
| Depositing User: | Andriamparany Edilbert RANOARIVONY |
| Date Deposited: | 02 Aug 2018 13:52 |
| Last Modified: | 02 Aug 2018 13:52 |
| URI: | http://thesisbank.jhia.ac.ke/id/eprint/8118 |
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